SoC: Software, Hardware, Nightmare, Bliss

Co-Verification of Hardware and Software for ARM SoC Design

SoC Synthesis with Automatic Hardware Software Interface Generation

Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C alo...

Hardware Partitioning Software for Dynamically Reconfigurable SoC Design

CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibilities of reconfiguration that the FPGA component can offer. Here, we present a temporal hardware partitioning software, included in a design methodology, that uses the reconfiguration possibilities of the FPGA for the ...

Software for automated SoC design based on Hardware/Software CoDesign Concept

Productivity gap on SoC design is a challenge to address in design method research area. Main research topics in this area address this problem using many schemes and methods. Software for automation in a system design and implementation is one solution to address design time efficiency. The second one is parallelism concept in hardware/software co-design. This approach addresses both design ti...

A Novel Discrete Hopfield Neural Network Approach for Hardware-Software Partitioning of RTOS in the SoC

The hardware-software automated partitioning of a RTOS in the SoC (SoC-RTOS partitioning) is a crucial step in the hardware-software co-design of SoC. First, a new model for SoC-RTOS partitioning is introduced in this paper, which can help in understanding the essence of the SoC-RTOS partitioning. Second, a discrete Hopfield neural network approach for implementing the SoC-RTOS partitioning is ...